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19-0670; Rev 0; 11/06
KIT ATION EVALU BLE AVAILA
Dual and Combinable Graphics Core Controller for Notebook Computers
General Description Features
o Dual-Output, Fixed-Frequency, Current-Mode Control o Combinable Output for Higher Currents o Dynamic Output Voltages with Automatic Fault Blanking and Transition Control o True Out-of-Phase Operation o True Differential Current Sense for Accurate Current Limit and Current Balance o 4V to 26V Input Range o 100kHz to 600kHz Switching Frequency o 0.5V to 2.5V Adjustable Outputs o Internal Integrator for High Output Accuracy o Stable with Low-ESR Output Capacitors o Independent Selectable PWM and Skip-Mode Operation o Independent Power-Good Outputs o Soft-Start and Soft-Stop o 2.5V Precision Reference o < 1A Typical Shutdown Current
MAX8775
The MAX8775 is a dual, step-down, interleaved, fixedfrequency, switch-mode power-supply (SMPS) controller with synchronous rectification. It is intended for GPU cores and I/O power generation in battery-powered systems. Flexible configuration allows the MAX8775 to operate as two independent single-phase regulators, or as one high-current two-phase regulator. Configured in separate mode, the MAX8775 provides power to two dynamic voltage rails, one for the GPU core and the other for the I/O power rail. Configured in combined mode, the MAX8775 functions as a twophase, high-current, single-output GPU core regulator, powering the high-performance GPU engines used in gaming machines and media center notebooks. The REFIN voltage setting allows for multiple dynamic output voltages required by the different GPU operating and sleep states. Automatic fault blanking, forced-PWM operation, and transition control are achieved by detecting the voltage change at REFIN. Fixed-frequency operation with 180 out-of-phase interleaving minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Current-mode control allows the use of low-ESR output capacitors. Internal integrators maintain high output accuracy over the full line-and-load range, in both forced-PWM mode and pulse-skipping mode. True differential current sensing provides accurate output current limit and current balance when operated in combined mode. Independent on/off and skip control allows flexible power sequencing and power management. Voltagecontrolled soft-start reduces inrush current. Soft-stop gradually ramps the output voltage down, preventing negative voltage dips.
Ordering Information
PART MAX8775ETJ+ TEMP RANGE -40C to +85C PINPACKAGE 32 Thin QFN 5mm x 5mm PKG CODE T3255-5
+Denotes lead-free package.
Pin Configuration
BST1 DL1 BST2 17 16 15 14 13 DH2 ON2 CSL2 CSH2 SKIP2 PGOOD2 CCI2 SLEW2 12 11 10 9 1 OVP1 2 OSC 3 REFIN1 4 VCC 5 AGND 6 REF 7 REFIN2 8 OVP2 VDD DL2 19 LX1 LX2 18
Applications
2 to 4 Li+ Cells Battery-Powered Devices Media Center and Gaming Notebooks GPU and I/O Power Supplies Tracking Output Power Supplies
TOP VIEW
24 DH1 25 ON1 26 CSL1 27 CSH1 28 SKIP1 29 PGOOD1 30 DTRANS 31 SLEW1 32
23
22
21
20
MAX8775
THIN QFN 5mm x 5mm
________________________________________________________________ Maxim Integrated Products
PGND
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
ABSOLUTE MAXIMUM RATINGS
VDD, VCC, CSH_, CSL_ to AGND............................-0.3V to +6V ON_, SKIP_, PGOOD_ to AGND ..............................-0.3V to +6V OVP_, REFIN_ to AGND ...........................................-0.3V to +6V DTRANS to AGND ....................................................-0.3V to +6V REF, OSC, SLEW_, CCI2 to AGND ...........-0.3V to (VCC + 0.3V) BST1, BST2 to AGND .............................................-0.3V to +36V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V) AGND to PGND .....................................................-0.3V to +0.3V REF Short Circuit to AGND.........................................Continuous REF Current ......................................................................+10mA Continuous Power Dissipation (TA = +70C) 32-Pin, 5mm x 5mm, Thin QFN (derate 21.3mW/C above +70C) .............................1702mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, SKIP_ = PGND = AGND, ON_ = VCC = 5V, separate mode, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES Input Voltage Range VCC Undervoltage Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) SMPS CONTROLLERS Output Voltage Accuracy Output Voltage-Adjust Range REFIN Operating Voltage-Adjust Range REFINOK Threshold REFIN Transient Detection Threshold Combined-Mode Enabled Threshold DC Load Regulation Line Regulation Error Switching-Frequency Accuracy (Note 3) Maximum Duty Factor Minimum On-Time fOSC DMAX tONMIN (Note 4) VREFIN2 Either SMPS, SKIP_ = VCC, zero to full load Either SMPS, 4V < VIN < 26V ROSC = 143k (fOSC = 300kHz nominal) ROSC = 71.5k (fOSC = 600kHz nominal) to 432k (fOSC = 99kHz nominal) -10 -15 91 93 150 With respect to REFIN_, VREFIN_ REFIN_ = 0.5V to 2.5V, VCSL_ SKIP_ = VCC or GND (Note 1) VCSL_ VREFIN_ Either SMPS (Note 2) Either SMPS (Note 2) Either SMPS 5mV (typ) hysteresis 3 -5 0.5 0.5 0.1 25 VCC 1 -0.1 0.03 +10 +15 % % ns VCC 0.4 0 +5 2.5 2.5 mV V V V mV V % %/V VIN VBIAS VUVLO ICC IDD VCC, VDD Rising edge, 50mV typical hysteresis CSL_ forced above their regulation points CSL_ forced above their regulation points, SKIP mode 4 4.5 4.1 4.25 1.5 <1 <1 <1 26 5.5 4.5 2.5 5 5 5 V V mA A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
ICC(SHDN) ON1 = ON2 = GND IDD(SHDN) ON1 = ON2 = GND
2
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Dual and Combinable Graphics Core Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, SKIP_ = PGND = AGND, ON_ = VCC = 5V, separate mode, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SMPS1 to SMPS2 Phase Shift Slew-Rate Current CURRENT LIMIT Current-Limit Threshold Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) Idle ModeTM Threshold REFERENCE (REF) Reference Voltage Reference Source Load Regulation Reference Sink Load Regulation REF Lockout Voltage CURRENT BALANCE Current-Balance Amplifier (GMI) Offset Current-Balance Amplifier (GMI) Transconductance FAULT DETECTION OVP_ Adjust Range Output Overvoltage Trip Threshold Output Overvoltage Fault Propagation Delay Output Undervoltage Protection Trip Threshold Output Undevoltage Fault Propagation Delay Output Undervoltage Protection Blanking Time PGOOD_ Lower Trip Threshold PGOOD_ Propagation Delay tPGOOD_ tUVP tBLANK tOVP VOVP_ Rising edge measured at CSL_, with respect to OVP_ set voltage 50mV overdrive Falling edge measured at CSL_, with respect to error comparator threshold 50mV overdrive From rising edge of ON_ Falling edge measured at CSL_, with respect to error comparator threshold, hysteresis = 1% Falling edge, 50mV overdrive -325 0.5 180 200 10 300 10 6144 -275 2.5 220 V mV s mV s 1/fSW [V(CSH1,CSL1) - V(CSH2,CSL2)] at ICCI = 0 ICCI/[V(CSH1,CSL1) - V(CSH2,CSL2)], VCCI = VOUT = 0.5V to 2.5V, and V(CSH_,CSL_) = -60.0mV to +60.0mV -2 +2 mV VREF VREF VCC = 4.5V to 5.5V, IREF = 0 IREF = 0A to 250A IREF = -50A VREF(UVLO) Rising edge, hysteresis = 100mV 2.3 TA = +25C to +85C TA = 0C to +85C 2.482 2.475 2.50 2.50 0.25 2.518 2.525 1.5 6 V mV mV V VLIMIT VNEG VZX IMIN VCSH_ - VCSL _ VCSH_ - VCSL _, SKIP_ = VCC VCSH_ - VCSL _, SKIP_ = GND VCSH_ - VCSL _, SKIP_ = GND 3.6 26 -43 30 -36 3 6 8.4 34 -29 mV mV mV mV ISLEW_ ISLEWSS_ SYMBOL CONDITIONS SMPS2 starts after SMPS1 During transition Startup and shutdown 4.0 0.70 MIN TYP 50 180 4.75 0.95 5.5 1.20 MAX UNITS % Deg A
MAX8775
200
S
-180
-150 10
-120
mV s
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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3
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, SKIP_ = PGND = AGND, ON_ = VCC = 5V, separate mode, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PGOOD_ Output Low Voltage PGOOD_ Leakage Current PGOOD_ Transition Blanking Time IPGOOD_ SYMBOL ISINK = 4mA High state, PGOOD_ forced to 5.5V Measured from the time CSL_ reaches the target voltage based on the slew rate set by CSLEW_ V(CCI2, REF), 0.5V VFB 2.5V TSHDN RDH RDL IDH IDL
(SOURCE)
CONDITIONS
MIN
TYP
MAX 0.4 1
UNITS V A s
20
Current-Balance Fault Comparator Thresholds Thermal-Shutdown Threshold GATE DRIVERS DH_ Gate Driver On-Resistance DL_ Gate Driver On-Resistance (Note 5) DH_ Gate Driver Source/ Sink Current DL_ Gate Driver Source Current DL_ Gate Driver Sink Current Dead Time Internal Boost Diode Switch RON LX_, BST_ Leakage Current INPUTS AND OUTPUTS Logic Input Current Logic Input-High Threshold Input Leakage Current
Lower threshold, 0.84VREF Upper threshold, 1.2VREF
2.0 2.9 +160 1.5 1.7 0.6 2 1.7 3.3 15 10 35 26 6.5 <2 -1 1.2 -0.15 1.7
2.2 V 3.0 C 5 5 3 A A A ns 9 20 +1 2.2 +0.15 A A V A
Hysteresis = 15C BST_ - LX_ forced to 5V (Note 5) DL_, high state DL_, low state DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DL_ forced to 2.5V DL_ to DH_ DH_ to DL_ Measure with 10mA of current VBST_ = VLX_ = 28V ON1, ON2, DTRANS, SKIP1, SKIP2 ON1, ON2, DTRANS, SKIP1, SKIP2, hysteresis = 225mV CSH_, CSL_, 0V, or VDD
IDL (SINK) tDEAD
4
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Dual and Combinable Graphics Core Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, SKIP_ = 0, ON_ = VCC = 5V, separate mode, TA = -40C to +85C, unless otherwise noted.) (Note 6)
PARAMETER INPUT SUPPLIES Input Voltage Range VCC Undervoltage Lockout Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) MAIN SMPS CONTROLLERS PWM_ Output Voltage Output Voltage Adjust Range REFIN Operating Voltage Adjust Range Combined Mode Enabled Switching Frequency Accuracy (Note 2) Maximum Duty Factor Slew-Rate Current CURRENT LIMIT Current-Limit Threshold REFERENCE (REF) Reference Voltage Reference Source Load Regulation Reference Sink Load Regulation CURRENT BALANCE Current-Balance Amplifier (GMI) Offset [V(CSH1,CSL1) - V(CSH2,CSL2)] at ICCI = 0 -3 +3 mV VREF VREF VCC = 4.5V to 5.5V, IREF = 0 IREF = 0A to 250A IREF = -50A 2.462 2.538 2 10 V mV mV VLIMIT VCSH_ - VCSL_ 25 35 mV With respect to REFIN_, VREFIN_ REFIN_ = 0.5V to 2.5V, VCSL_ SKIP_ = VCC or GND (Note 1) VCSL_ VREFIN_ VREFIN2 ROSC = 143k (fOSC = 300kHz nominal) fOSC DMAX ISLEW_ During transition ISLEWSS_ Startup and shutdown ROSC = 71.5k (fOSC = 600kHz nominal) to 432k (fOSC = 99kHz nominal) Either SMPS (Note 2) Either SMPS (Note 2) -7.5 0.5 0.5 3 -15 -20 90 3.75 0.7 5.50 1.2 +15 +20 % % A +7.5 2.5 2.5 mV V V V VIN VBIAS VUVLO ICC IDD VCC, VDD Rising edge, 200mV typical hysteresis CSL_ forced above their regulation points CSL_ forced above their regulation points ON1 = ON2 = GND ON1 = ON2 = GND 4 4.5 4.1 26 5.5 4.5 2.5 5 5 5 V V mA A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX8775
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5
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, SKIP_ = 0, ON_ = VCC = 5V, separate mode, TA = -40C to +85C, unless otherwise noted.) (Note 6)
PARAMETER FAULT DETECTION OVP_ Adjust Range Output Overvoltage Trip Threshold Output Undervoltage Protection Trip Threshold PGOOD_ Lower Trip Threshold PGOOD_ Output Low Voltage Current-Balance Fault Comparator Thresholds GATE DRIVERS DH_ Gate Driver On-Resistance DL_ Gate Driver On-Resistance (Note 4) INPUTS AND OUTPUTS Logic Input-High Threshold ON1, ON2, DTRANS, SKIP1, SKIP2, hysteresis = 225mV 1.2 2.2 V RDH RDL BST_ - LX_ forced to 5V (Note 4) DL_, high state DL_, low state 5 5 3 VOVP_ Rising edge measured at CSL_, with respect to OVP_ set voltage Falling edge measured at CSL_, with respect to error comparator threshold Falling edge measured at CSL_ with respect to error comparator threshold, hysteresis = 1% ISINK = 4mA V(CCI2, REF), 0.5V VFB 2.5V Lower threshold, 0.84VREF Upper threshold, 1.2VREF 2.0 2.9 0.5 180 275 2.5 220 325 V mV mV SYMBOL CONDITIONS MIN TYP MAX UNITS
-180
-120 0.4 2.2
mV V
mV 3.1
Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the error comparator threshold by 50% of the ripple. Note 2: Operation below 0.5V but above the REFOK threshold is allowed, but the accuracy is not guaranteed. Note 3: The MAX8775 cannot operate over all combinations of frequency, input voltage (VIN), and output voltage. For large input-tooutput differentials and high switching-frequency settings, the required on-time might be too short to maintain the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are measured from the 50% point to the 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 4: Specifications are guaranteed by design, not production tested. Note 5: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin QFN package. Note 6: Specifications to TA = -40C to +85C are guaranteed by design, not production tested.
6
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Dual and Combinable Graphics Core Controller for Notebook Computers
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, TA = +25C, unless otherwise noted.)
1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.5V)
MAX8775 toc01
MAX8775
2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.5V)
MAX8775 toc02
EFFICIENCY vs. LOAD CURRENT (VOUT = 1.5V)
MAX8775 toc03
100 90 EFFICIENCY (%) 80 70 60 50 40 0.1 1 VIN = 7V, PWM VIN = 12V, PWM VIN = 20V, PWM VIN = 7V, SKIP VIN = 12V, SKIP VIN = 20V, SKIP 10
100 90 EFFICIENCY (%) 80 70 60 50 40 0.1 1 VIN = 7V, PWM VIN = 12V, PWM VIN = 20V, PWM VIN = 7V, SKIP VIN = 12V, SKIP VIN = 20V, SKIP 10
100 90 EFFICIENCY (%) 80 70 60 50 40 0.1 1 10 VIN = 12V VOUT = 1.5V 1-PHASE, PWM 2-PHASE, PWM 1-PHASE, SKIP 2-PHASE, SKIP
100
100
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8775 toc04
EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2V)
MAX8775 toc05
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP MODE)
MAX8775 toc06
1.505
100 90 EFFICIENCY (%) 80 70 60 50 40 VIN = 12V VOUT = 1.2V 1-PHASE, PWM 2-PHASE, PWM 1-PHASE, SKIP 2-PHASE, SKIP 0.1 1 10
10 ICC SUPPLY CURRENT (mA) 1 IDD
1.503 OUTPUT VOLTAGE (V)
1.501
0.1 IIN
1.499 VIN = 12V VOUT = 1.5V PWM MODE SKIP MODE 1.495 0 5 10 15 20 25 30 LOAD CURRENT (A)
0.01
1.497
0.001 100 0 4 8 12 16 20 24 LOAD CURRENT (A) INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (1-PHASE PWM MODE)
MAX8775 toc07
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (2-PHASE PWM MODE)
MAX8775 toc08
CURRENT-SENSE OFFSET vs. LOAD CURRENT (2-PHASE PWM MODE)
MAX8775 toc09
100
100
1.0 CURRENT BALANCE OFFSET (mV)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
IDD
IIN
0.5
IDD 10
IIN
10
0
-0.5
ICC 1 0 4 8 12 16 20 24 INPUT VOLTAGE (V) 1 0 4 8
ICC -1.0 12 16 20 24 0 5 10 15 20 25 30 INPUT VOLTAGE (V) LOAD CURRENT (A)
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, TA = +25C, unless otherwise noted.)
STARTUP/SHUTDOWN-- SAME SLEW RATE
MAX8775 toc12
STARTUP WAVEFORMS
MAX8775 toc10
SHUTDOWN WAVEFORMS
MAX8775 toc11
A 0 0 B C D 0 0 1.5V 0 0 5A E 0 200s/div A: ON1, 5V/div B: DL1, 5V/div C: VOUT1, 1V/div D: PGOOD1, 5V/div E: ILX1, 5A/div 0 200s/div A: ON1, 5V/div B: DL1, 5V/div C: VOUT1, 1V/div D: PGOOD1, 5V/div E: ILX1, 5A/div
A B
0
A
0 0 0 5A C D 0 5V 0 5V 0 400s/div A: ON1, ON2, 5V/div D: PGOOD1, 5V/div B: VOUT1, 1V/div E: PGOOD2, 5V/div C: VOUT2, 1V/div CSLEW1 = CSLEW2 = 470pF RLOAD1 = RLOAD2 = 1
B C
D E
E
SKIP1 = GND, RLOAD1 = 1, VIN = 12V
SKIP1 = GND, RLOAD1 = 1, VIN = 12V
STARTUP/SHUTDOWN-- SAME START TIME
MAX8775 toc13
LOAD TRANSIENT (SEPARATE MODE)
MAX8775 toc14
LOAD TRANSIENT (COMBINED MODE)
MAX8775 toc15
0
A 1.2V 5V
A
1.5V 10A
A
0 0 5V 0 5V 0 400s/div A: ON1, ON2, 5V/div D: PGOOD1, 5V/div B: VOUT1, 1V/div E: PGOOD2, 5V/div C: VOUT2, 1V/div CSLEW1 = 470pF, CSLEW2 = 600pF RLOAD1 = RLOAD2 = 1
B 0 C 12V 0 D 10A E 0 20s/div C: LX1, 10V/div A: VOUT1, 100mV/div D: ILX1, 10A/div B: DL1, 5V/div VIN = 12V, VOUT1 = 1.2V SKIP1 = GND IOUT1 = 1A TO 11A TO 1A
B
B
0 12V
C 0 12V D
C
D 0 20s/div C: LX1, 10V/div A: VOUT1, 100mV/div D: LX2, 10V/div B: ILX1, 10A/div VIN = 12V, VOUT = 1.5V IOUT1 = 5A TO 25A TO 5A
8
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Dual and Combinable Graphics Core Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP_ = GND, TA = +25C, unless otherwise noted.)
REFIN TRANSITION WAVEFORMS (DTRANS = VCC)
MAX8775 toc17
MAX8775
SWITCHING WAVEFORMS
MAX8775 toc16
REFIN TRANSITION WAVEFORMS (DTRANS = GND)
MAX8775 toc18
12V A 0 12V B 0 1.5V 1.2V C D E 0 2s/div D: VOUT2, 50mV/div A: LX1, 10V/div B: LX2, 10V/div E: VIN, 50mV/div C: VOUT1, 50mV/div VIN = 12V, VOUT1 = 1.5V, VOUT2 = 1.2V IOUT1 = 5A, IOUT2 = 5A 100s/div A: REFIN1, 500mV/div C: VOUT1, 200mV/div B: LX1, 10A/div D: ILX1, 10A/div VIN = 12V, VREFIN1 = 1.2V TO 1.5V TO 1.2V IOUT1 = 1A SKIP1 = GND 1.2V 10A 12V D 40s/div A: REFIN1, 500mV/div C: VOUT1, 200mV/div B: LX1, 10A/div D: ILX1, 10A/div VIN = 12V, VREFIN1 = 1.2V TO 1.5V TO 1.2V IOUT1 = 1A SKIP1 = GND C 1.5V 1.2V 12V B 0 1.5V A 1.5V 1.2V 12V 0 1.5V 1.2V 0 C B A
D
COMBINED-MODE PHASE TRANSITION
MAX8775 toc19
COMBINED-MODE PHASE TRANSITION
MAX8775 toc20
1.2V
A
1.2V
A
0 12V
B
0 10A
B
C 0 12V D 0 10s/div C: LX1, 10V/div A: VOUT, 50mV/div D: LX2, 10V/div B: ON2, 5V/div VIN = 12V, VOUT = 1.2V IOUT = 10A 10A 0 10s/div A: VOUT, 50mV/div B: ON2, 5V/div VIN = 12V, VOUT = 1.2V IOUT = 10A C: ILX2, 10A/div D: ILX1, 10A/div 0
C
D
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9
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
Pin Description
PIN 1 NAME OVP1 FUNCTION SMPS1 Overvoltage Adjust Input. The overvoltage trip threshold for SMPS1 is 200mV above the voltage at OVP1. Connect OVP1 to VCC to disable OVP for SMPS1. OVP1 sets the overvoltage threshold for both phases in combined mode. Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and AGND to set the switching frequency (per phase): fOSC = 300kHz x 143k / ROSC A 71.5k to 432k corresponds to switching frequencies of 600kHz to 100kHz, respectively. Ensure the minimum on-time requirement is met for the selected frequency. 3 4 5 REFIN1 VCC AGND SMPS1 External Reference Input. REFIN1 sets the output regulation voltage (VCSL1 = VREFIN1). REFIN1 sets the output regulation voltage in combined mode (VCSL1 = VCSL2 = VREFIN1). Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 10 resistor. Bypass VCC to AGND with a 1F or greater ceramic capacitor. Analog Ground. Connect backside pad to AGND. 2.5V Reference Voltage Output. Bypass REF to AGND with a 0.1F or greater ceramic capacitor. The maximum value of this cap is 1F. The reference can source up to 250A. Loading REF degrades output-voltage accuracy according to the REF load-regulation error (see Typical Operating Characteristics). The reference shuts down when both ON1 and ON2 are low. SMPS2 External Reference Input. REFIN2 sets the feedback regulation voltage (VCSL2 = VREFIN2). Connect REFIN2 to VCC to select combined mode. See OVP2 pin connection below. SMPS2 Overvoltage Adjust Input. The overvoltage trip threshold for SMPS2 is 200mV above the voltage at OVP2. Connect OVP2 to VCC to disable OVP for SMPS2. Connect OVP2 to REF in combined mode when OVP is enabled. Connect OVP2 to VCC in combined mode when OVP is disabled. SMPS2 Slew-Rate Control. Connect a capacitor from SLEW2 to AGND to set the SMPS2 slew rate: Slew Rate (VOUT2 / t) = ISLEW2 / CSLEW2 During startup and shutdown, SMPS2 ramps at 1/5 the programmed slew rate. Connect SLEW2 to SLEW1 in combined mode. 10 CCI2 Current-Balance Compensation for SMPS2. When combining SMPS1 and SMP2, connect a 47pF capacitor between CCI2 and AGND. Leave CCI2 open when operating SMPS1 and SMPS2 separately.
2
OSC
6
REF
7
REFIN2
8
OVP2
9
SLEW2
11
SMPS2 Open-Drain Power-Good Output. PGOOD2 is low when SMPS2 is more than 150mV below its regulation PGOOD2 threshold, when a 0V fault occurs, during soft-start, and in shutdown. PGOOD2 is the current-balance fault indicator when operating in combined mode. SKIP2 Low-Noise Mode Control for SMPS2. Connect SKIP2 to GND for normal Idle Mode (pulse-skipping) operation or to VCC for PWM mode (fixed frequency). SKIP2 is ignored in combined mode. Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the current-sense element. Figure 10 describes two different current-sensing options. Negative Current-Sense and Feedback Input for SMPS2. Connect to the negative terminal of the current-sense element. CSL2 regulates to REFIN2. Figure 10 describes two different current-sensing options. CSL2 regulates to REFIN1 in combined mode. SMPS2 Enable Input. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down SMPS2. When both outputs are combined, ON1 is the master control input to enable/disable the combined output, while ON2 enables/disables phase 2, allowing 1- or 2-phase operation.
12
13
CSH2
14
CSL2
15
ON2
10
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Dual and Combinable Graphics Core Controller for Notebook Computers
Pin Description (continued)
PIN 16 17 18 19 20 21 22 23 24 25 26 NAME DH2 BST2 LX2 DL2 PGND VDD DL1 LX1 BST1 DH1 ON1 FUNCTION High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2. Boost Flying-Capacitor Connection for SMPS2. Connect to an external capacitor as shown in Figure 1. An optional resistor in series with BST2 allows the DH2 turn-on current to be adjusted. Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2 is the lower supply rail for the DH2 high-side gate driver. Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to VDD. Power Ground Supply Voltage Input for the DL_ Gate Drivers. Connect to a 5V supply. Bypass VDD to AGND with a 1F or greater ceramic capacitor. Low-Side Gate-Driver Output for SMPS1. DL1 swings from PGND to VDD. Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1 is the lower supply rail for the DH1 high-side gate driver. Boost Flying-Capacitor Connection for SMPS1. Connect to an external capacitor as shown in Figure 1. An optional resistor in series with BST1 allows the DH1 turn-on current to be adjusted. High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1. SMPS1 Enable Input. Drive ON1 high to enable SMPS1. Drive ON1 low to shut down SMPS1. When both outputs are combined, ON1 is the master control signal to enable/disable the combined output, while ON2 enables/disables phase 2, allowing 1- or 2-phase operation. Negative Current-Sense and Feedback Input for SMPS1. Connect to the negative terminal of the current-sense element. CSL1 regulates to REFIN1. Figure 10 describes two different current-sensing options. Positive Current-Sense Input for SMPS1. Connect to the positive terminal of the current-sense element. Figure 10 describes two different current-sensing options. Low-Noise Mode Control for SMPS1. Connect SKIP1 to GND for normal Idle Mode (pulse-skipping) operation or to VCC for PWM mode (fixed frequency). When both outputs are combined, SKIP2 is ignored and SKIP1 sets the skip function for both SMPS1 and SMPS2.
MAX8775
27 28
CSL1 CSH1
29
SKIP1
30
SMPS1 Open-Drain Power-Good Output. PGOOD1 is low when SMPS1 is more than 150mV below its regulation PGOOD1 threshold, when a 0V fault occurs, during soft-start, and in shutdown. PGOOD1 is the voltage-regulation fault indicator when operating in combined mode. Forced-Downward Transient Disable Input. Connect DTRANS to VCC to disable the forced-downward transition detection feature when operating in pulse-skipping mode, allowing the output to fall at a rate determined by the DTRANS load current and total output capacitance. Connect DTRANS to AGND to enable the forced downward-transition detection feature. SMPS1 Slew-Rate Control. Connect a capacitor from SLEW1 to AGND to set the SMPS1 slew rate: Slew Rate (VOUT1 / t) = ISLEW1 / CSLEW1
31
32
SLEW1
During startup and shutdown, SMPS1 ramps at 1/5 the programmed slew rate. In combined mode, the slew rate is set by both SLEW1 and SLEW2. Connect SLEW1 and SLEW2 together in combined mode: Combined Slew Rate (VOUT / t) = (ISLEW1 + ISLEW2) / (CSLEW1 + CSLEW2) Exposed Backside Pad. Connect the exposed backside pad to AGND.
--
EP
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11
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
Detailed Description
The MAX8775 is a dual fixed-frequency step-down controller for low-voltage I/O and graphics core (GPU) supplies. It can be configured as two separate regulators generating two independent outputs. Alternatively, the MAX8775 can be configured in combined mode as a
R7 10 C4 1F CREF 0.1F REF DH1 ROSC 154k OSC CSLEW1 470pF SLEW1 CSLEW2 470pF SLEW2 GND CSL1 DTRANS +5V R8 100k R9 100k PGOOD1 PGOOD2 R1 100k REF R3 249k REFIN1 VOUT1(L) VOUT1(H) R2 150k CSL2 OVP1 CSH2 C5 2.2nF C6 4.7nF DH2 BST2 LX1 DL1 PGND CSH1 C1 2.2nF C2 4.7nF NH2 CBST2 0.1F LX2 DL2 R12 150 R13 10 NL2 DL2 COUT2 (2) 330F CIN2 R10 150 R11 10 INPUT VIN 7V TO 20V NL1 DL1 BST1 CBST1 0.1F L1 0.88H RSENSE1 1.5m VOUT1 1.5V/1.2V 15A COUT1 (2) 330F NH1 C3 2.2F VCC VDD CIN1
two-phase, single-output, high-current regulator, powering the high-performance graphics cores used in game machines and media center notebooks. The standard applications circuit (Figure 1) generates dynamically adjustable output voltages on both outputs. REFIN voltage setting allows for multiple dynamic
+5V
INPUT VIN 7V TO 20V
MAX8775
L2 0.88H
RSENSE2 1.5m
VOUT2 1.5V/1.2V 15A
CCI2 R4 100k REF R6 249k REFIN2 VOUT2(L) VOUT2(H) R5 150k OVP2 ON2 SKIP1 SKIP2 EP ON1
NOT USED ANALOG GROUND POWER GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 1. MAX8775 Separate Output Typical Operating Circuit
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Dual and Combinable Graphics Core Controller for Notebook Computers
output voltages required by the different GPU operating and sleep states. Automatic fault blanking, forced-PWM operation, and transition control are achieved by detecting the voltage change at REFIN. The interleaved, fixed-frequency architecture provides 180 out-of-phase operation to reduce the input capacitance required to meet the RMS input-current ratings.
R7 10 C4 1F CREF 0.1F REF DH1 ROSC 154k OSC CSLEW 1000pF LX1 SLEW1 DL1 PGND SLEW2 CSH1 GND CSL1 DTRANS +5V R8 100k R9 100k PGOOD1 PGOOD2 R1 100k REF R3 249k REFIN1 VOUT(L) VOUT(H) R2 150k CSL2 OVP1 CSH2 C5 2.2nF C6 4.7nF C1 2.2nF C2 4.7nF CIN2 DH2 BST2 NH2 CBST2 0.1F LX2 DL2 R12 100 R13 10 NL2 DL2 L2 0.56H RSENSE2 1.0m R10 100 R11 10 INPUT VIN 7V TO 20V COUT (4) 330F NL1 DL1 BST1 CBST1 0.1F L1 0.56H RSENSE1 1.0m VOUT 1.5V/1.2V 40A NH1 C3 2.2F VCC VDD CIN1
Each controller consists of a multi-input PWM comparator, high-side and low-side gate drivers, fault protection, power-good detection, soft-start, and shutdown logic. Current-mode control allows the use of low-ESR output capacitors. In combined mode (Figure 2), phase 1 provides the main voltage-control loop while phase 2 maintains the
MAX8775
+5V
INPUT VIN 7V TO 20V
MAX8775
CCCI2 47pF
CCI2 ANALOG GROUND ON1 CONNECT REFIN2 TO VCC AND OVP2 TO REF OR VCC FOR COMBINED-MODE OPERATION REF OVP2 ON2 VCC REFIN2 SKIP1 SKIP2 EP NOT USED POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 2. MAX8775 Combined-Output Typical Operating Circuit
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
current balance. PGOOD1 indicates when the combined output is in regulation, while PGOOD2 indicates the currents in both phases are balanced. Phase 2 can be enabled or disabled based on the load current required, maximizing efficiency over the full output current range. Figure 3 is the MAX8775 functional block diagram.
VIN
+5V BIAS VCC REF VDD OSC BST2 BST1 PWM DRIVER BLOCK SMPS 1 SMPS 2
2.5V REF
MAX8775
OSC
DH1 LX1 DL1
DH2
LX2 DL2
SLOPE COMP
4X
CSH2 CSL2
CSH1 CSL1 SKIP1 DTRANS PGOOD1 REFIN1 SLEW1 SLEW POWERGOOD REFIN TRANS REFIN
SKIP2 CCI2 PGOOD 2
REFIN2 SLEW2
ON2 ON1 OVP1 SOFT-START/ SOFT-STOP OVP OVP2
AGND
PGND
Figure 3. MAX8775 Functional Block Diagram
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Dual and Combinable Graphics Core Controller for Notebook Computers
Table 1. Component Selection for Standard Applications
COMPONENT MODE Switching Frequency CIN_, Input Capacitor COUT_, Output Capacitor NH_ High-Side MOSFET NL_ Low-Side MOSFET VIN = 7V TO 24V VOUT1 = 1.0V - 1.5V / 15A SEPARATE (FIGURE 1) 280kHz (2) 10F, 25V Taiyo Yuden TMK432BJ106KM (2) 330F, 6.3V, 7m, low-ESR capacitor Panasonic EEFSD0D331XR (1) Vishay/Siliconix SI7634DP (1) Vishay/Siliconix SI7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 0.88H, 18A, 2.1m NEC/Tokin MPC1040LR88 1.5m, 1W, 2512 Panasonic ERJM1WTJ1M5U VIN = 7V TO 24V VOUT2 = 1.8V / 10A SEPARATE 280kHz (1) 10F, 25V Taiyo Yuden TMK432BJ106KM (1) 330F, 6.3V, 7m, low-ESR capacitor Panasonic EEFSD0D331XR (1) International Rectifier IRF7811W (1) Vishay/Siliconix SI7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 1.8H, 13.8A, 6.2m Sumida CDEP105(S)-1R8 2m, 0.5W, 2010 Vishay WSL20102L000F VIN = 7V TO 24V VOUT1 = 1.0V - 1.5V / 40A COMBINED (FIGURE 2) 280kHz (4) 10F, 25V Taiyo Yuden TMK432BJ106KM (4) 330F, 6.3V, 7m, low-ESR capacitor Panasonic EEFSD0D331XR (1) Vishay/Siliconix SI7634DP (2) Vishay/Siliconix SI7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 0.56_H, 26A, 1.3m NEC/Tokin MPC1040LR56 Panasonic ETQP4LR56WFC 1.0m, 1W, 2512 Panasonic ERJM1WTJ1M0U
MAX8775
DL_ Schottky Rectifier
L_ Inductor
Current-Sense RSENSE_
Table 2. Component Suppliers
SUPPLIER AVX Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet WEBSITE www.avx.com www.centralsemi.com www.coilcraft.com www.coiltronics.com www.fairchildsemi.com www.irf.com www.kemet.com SUPPLIER Panasonic Sanyo Sumida Taiyo Yuden TDK TOKO Vishay (Dale, Siliconix) WEBSITE www.panasonic.com/industrial www.secc.co.jp www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.vishay.com
See Table 1 for component selections and Table 2 for the component manufacturers.
SMPS 5V Bias Supply (VCC and VDD) The MAX8775 SMPSs require a 5V bias supply in addition to the high-power input supply (battery or AC adapter). VDD is the power rail for the MOSFET gate drive, and VCC is the power rail for the IC. Connect the external 4.5V to 5.5V supply directly to VDD and connect V DD to V CC through an RC filter, as shown in Figure 1. The maximum supply current required is: IBIAS = ICC + fSW (QG(NL1) + QG1(NH1) +QG2(NL2) + QG2(NH2)) = 1.8mA to 40mA
where ICC is 1.8mA, fSW is the switching frequency, and QG_is the MOSFET data sheet's total gate-charge specification limits at VGS = 5V.
Reference (REF)
The 2.5V reference is accurate to 1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.1F or greater ceramic capacitor. The reference sources up to 250A and sinks 50A to support external loads.
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15
Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
SMPS Detailed Description
SMPS Enable Controls (ON1, ON2)
ON1 and ON2 provide independent control of output soft-start and soft-shutdown. This allows flexible control of startup and shutdown sequencing. The outputs may be started simultaneously, sequentially, or independently. To provide sequential startup, connect ON_ of one regulator to PGOOD_ of the other. For example, with ON1 connected to PGOOD2, OUT1 soft-starts after OUT2 is in regulation. Additionally, tracking and ratiometric startup and shutdown can be achieved using the SLEW_ capacitors. See the Startup Sequencing section. When configured in combined mode (REFIN2 = VCC), ON1 is the master control input that enables/disables the combined output. ON2 enables/disables only the 2nd phase, allowing dynamic switching between onephase and two-phase operation. Toggle ON_ low to clear the overvoltage, undervoltage, and thermal-fault latches. 10mV/s, and a soft-start, soft-shutdown slew rate of approximately 2mV/s. Soft-shutdown begins after ON_ goes low, an output undervoltage fault, or a thermal fault. During soft-shutdown, the output is ramped down to 0V at 1/5 the programmed slew rate, reducing negative inductor currents that can cause negative voltages on the output. At the end of soft-shutdown, DL_ is driven high until startup is again triggered by a rising edge of ON_. The reference is turned off when both outputs have been shut down. When configured in separate mode, the two outputs are independent. A fault at one output does not trigger shutdown of the other.
Soft-Start and Soft-Shutdown Soft-start begins when ON_ is driven high and REF is in regulation. During soft-start, the output is ramped up from 0V to the final set voltage at 1/5 the slew rate programmed by the capacitor at the SLEW_ pin. This reduces inrush current and provides a predictable ramp-up time for power sequencing: Soft-Start/Stop Slew Rate (VOUT_ / t) = ISLEWSS_ / CSLEW_ where I SLEWSS_ is 0.95A (typ), and C SLEW_ is the capacitor across the SLEW_ pin and AGND. A 470pF capacitor programs a slew rate of approximately
Startup Sequencing Individually programmable slew-rate control, on/off control, and power-good outputs allow flexible configuration of the MAX8775 for different power-up sequencing. This is useful in applications where one power rail needs to come up after another, track another rail, or reach regulation at about the same time. Figures 4, 5, and 6 show three configurations for startup sequencing.
Fixed-Frequency, Current-Mode PWM Controller
The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums three signals: the output voltage-error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (Figure 3). The MAX8775 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage
REF ON1 CREF REF REFIN1 REFIN2 MAX8775 VOUT1 1/5 PROGRAMMED SLEW RATE PGOOD1 = ON2 PGOOD2 DELAYED STARTUP/SHUTDOWN TIMING CSLEW1 = CSLEW2 SLEW2 VOUT2 1/5 PROGRAMMED SLEW RATE REFIN2 REFIN1
20s 20s
AGND SLEW1
Figure 4. MAX8775 Delayed Startup/Shutdown Timing
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
REF ON1 = ON2 CREF REF REFIN2 REFIN1 VOUT2 1/5 PROGRAMMED SLEW RATE PGOOD1 PGOOD2 TRACKING STARTUP/SHUTDOWN TIMING CSLEW1 = CSLEW2 SLEW2 20s 20s SLEW1 VOUT1 REFIN2 MAX8775 1/5 PROGRAMMED SLEW RATE REFIN1
AGND
Figure 5. MAX8775 Tracking Startup/Shutdown Timing
REF ON1 = ON2 CREF REF REFIN2 REFIN1 VOUT2 1/5 PROGRAMMED SLEW RATE PGOOD1 PGOOD2 20s SLEW1 RATIOMETRIC STARTUP/SHUTDOWN TIMING CSLEW1 > CSLEW2 SLEW2 VOUT1 REFIN2 MAX8775 1/5 PROGRAMMED SLEW RATE REFIN1
AGND
Figure 6. MAX8775 Ratiometric Startup/Shutdown Timing
without a traditional error amplifier and the phase shift associated with it. The MAX8775 uses a relatively low loop gain, allowing the use of lower cost output capacitors. The relative gain of the voltage comparator to the current comparator is internally fixed at 4:1. The high current gain results in stable operation even with low-output ESR capacitors. An internal integrator corrects for any loadregulation error caused by the high current gain. The low value of loop gain helps reduce output filter capacitor size and cost by shifting the unity-gain crossover frequency to a lower level.
Frequency Selection (FSEL) The OSC input programs the PWM mode switching frequency. Connect a resistor (ROSC) between OSC and AGND to set the switching frequency (per phase): fSW = 300kHz x 143k / ROSC
ROSC values between 71.5k and 432k correspond to switching frequencies of 600kHz to 100kHz, respectively. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower. Low-frequency (100kHz) operation offers the best overall efficiency at the expense of component size and board space.
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
When selecting a switching frequency, the minimum ontime at the highest input voltage and lowest output voltage must be greater than the 150ns (max) minimum on-time specification in the Electrical Characteristics table: VOUT(MIN) / VIN(MAX) x TSW > tON(MIN) A good rule is to choose a minimum on-time of at least 200ns. When in pulse-skipping operation SKIP_ = GND, the minimum on-time must take into consideration the time needed for proper skip-mode operation. The on-time for a skip pulse must be greater than the 150ns (max) minimum on-time specification in the Electrical Characteristics table: L x VIMIN t ON(MIN) RSENSE x (VIN(MAX) - VOUT(MIN) ) current-sense voltage exceeds the Idle Mode currentsense threshold. Under light-load conditions, the ontime duration depends solely on the Idle Mode current-sense threshold, which is 20% (SKIP_ = GND) of the full load current-limit threshold. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions.
Forced-PWM Mode
To maintain low-noise, fixed-frequency operation, drive SKIP_ high to put the output into forced-PWM mode. This disables the zero crossing comparator and allows negative inductor current. During forced-PWM mode, the switching frequency remains constant and the noload supply current is typically between 20mA and 40mA per phase, depending on external MOSFETs and switching frequency.
Light-Load Operation Control (SKIP_)
The MAX8775 includes SKIP_ inputs, which enable the corresponding outputs to operate in discontinuous mode. Connect SKIP_ to GND to enable the zero-crossing comparators of either controller. When the zerocrossing comparator is enabled, the controller forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. During skip mode, the VDD current consumption is reduced and efficiency is improved. In combined mode, SKIP2 is unused, and SKIP1 sets the operating mode for both phases. At very light loads, onephase and two-phase pulse-skipping operation have about the same efficiency (see the Efficiency vs. Load Current (V OUT =1.5V) graph in Typical Operating Characteristics). Keeping the MAX8775 in two-phase skip allows it to dynamically respond to a full-load transient without requiring any system level-control signal to indicate the state of the GPU core.
Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 7). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across CSH_ and CSL_. Once VCSH_ - VCSL _ drops below the 3mV zero-crossing, current-sense threshold, the comparator forces DL_ low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the "critical-conduction" point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is determined by:
ILOAD(SKIP) = (VIN - VOUT )VOUT 2LVINfOSC
tON(SKIP) = INDUCTOR CURRENT
VOUT VINfOSC ILOAD(SKIP)
ILOAD = ILOAD(SKIP) 2
Idle Mode Current-Sense Threshold When pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the
18
0 ON-TIME
TIME
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
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Dual and Combinable Graphics Core Controller for Notebook Computers
In combined-mode operation, since the load is shared between two phases, the load current at which PFM/PWM crossover occurs is twice that of each phase's crossover current. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductance. Generally, low inductance produces a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). In combined mode (REFIN2 = VCC), REFIN1 sets the voltage of the combined output.
MAX8775
Internal Integrator The MAX8775 includes an internal transconductance amplifier that integrates the feedback voltage and provides fine adjustment to the regulation voltage, allowing accurate DC output-voltage regulation regardless of the output ripple voltage. When the inductor conducts continuously, the MAX8775 regulates the peak of the output ripple. The internal integrator corrects for errors due to ESR ripple voltage, slope compensation, and current-sense load regulation, maintaining high DC accuracy throughout the full load range, including lightload operation while in pulse-skipping mode. Dynamic Output Voltages The MAX8775 controller automatically detects upward transitions of 25mV at REFIN_, enters forced-PWM operation, and blanks the power-good thresholds until 20s after the output reaches the new regulation target. The MAX8775 slews the output up at a rate set by the slew capacitor CSLEW_: Slew Rate (VOUT_ / t) = ISLEW_ / CSLEW_ where I SLEW_ is 4.75A (typ), and C SLEW_ is the capacitor across the SLEW_ pin and AGND. A 470pF capacitor programs a slew rate of approximately 10mV/s.
Setting DTRANS low enables the automatic REFIN_ detection downward transitions (Figure 8). This feature is especially useful as it allows the MAX8775 to be set in the high-efficiency, pulse-skipping operation (SKIP_ = low), while voltage transitions are automatically taken care of by the MAX8775. Forced downward transitions return the energy from the output capacitors back to the input reservoir.
OV THRESHOLD
Output Voltage
The MAX8775 regulates each output to the voltage set at REFIN_ by sensing the CSL_ pin. Changing the voltage at REFIN_ allows the MAX8775 to be used in applications that require dynamic output voltage changes between two or more set points. Figure 1 shows a dynamically adjustable resistive voltage-divider network at REFIN_. Using system control signals to drive the gate(s) of small-signal MOSFETs, resistors can be switched in and out of the REFIN_ resistor-divider, dynamically changing the voltage at REFIN_. The main output voltage is determined by the following equation: REQ VOUT(PWM) = VREF REQ + RTOP where R EQ is the equivalent resistance between REFIN_ and ground, and R TOP is the resistance between REFIN_ and REF (see Figures 1 and 2).
VOUT(HIGH) PGOOD THRESHOLD TRACKING OV VOUT(LOW) REFIN(HIGH) REFIN MODE DH PGOOD BLANK HIGH-Z BLANK HIGH-Z PULSE SKIP REFIN(LOW) FORCED-PWM VOUT 20s
20s PULSE SKIP FORCED-PWM PULSE SKIP
Figure 8. REFIN Transition (Skip Mode, Downward Transition Enabled)
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Dual and Combinable Graphics Core Controller for Notebook Computers
Setting DTRANS high disables the forced downward REFIN_ transition. This allows the output voltage to drift down at a rate determined by the load current and the total output capacitance (Figure 9). Downward transitions in some systems are less critical from a timing standpoint because the voltage is above the new lower target. The power consumed in moving the output voltage to the new lower level in a forced manner where the energy is returned to the input with DTRANS low, needs to be weighed against the higher leakage power loss when the voltage drifts down with DTRANS high. Since the efficiency calculations require complex workload duty factors to be taken into consideration, a simple setting of the DTRANS pin allows testing and comparison in both modes to determine which mode offers best efficiency. Table 3 is the DTRANS operating modes truth table.
MAX8775
current between two phases, distributing the power dissipation over several power components. The MAX8775 is configured in combined mode by connecting REFIN2 to VCC and OVP2 to REF or VCC. See Figure 2 for the combined-mode standard application schematic. See the OVP2 connection requirements in the Pin Description table.
Combined-Mode Operation
Combined Mode (REFIN2 = VCC) Combined-mode operation allows the MAX8775 to support even higher output currents by sharing the load
Phase Transition (ON2) While in combined mode, ON1 functions as the master control signal that enables/disables the combined output. ON2 enables/disables only phase 2. This allows for flexible power management where phase 2 can be disabled at lighter loads, operating at the most optimal point of the efficiency curve. The MAX8775 does not override the ON2 signal during startup and shutdown. If ON2 is low during startup and shutdown, the MAX8775 operates only in one phase. Since the startup and shutdown slew rates are slow and the load currents are typically low, one-phase operation during startup and shutdown might be possible. Actual system testing and characterization of system load is required to guarantee operation in this mode.
FIXED OV THRESHOLD
VOUT(HIGH)
OUTPUT DRAGGED DOWN BY LOAD 20s
PGOOD THRESHOLD
VOUT(LOW) REFIN(HIGH) REFIN MODE DH PGOOD BLANK HIGH-Z PULSE SKIP REFIN(LOW)
TARGET
20s PWM MODE PULSE SKIP
BLANK HIGH-Z
REFIN TRANSITION (SKIP MODE, DOWNWARD TRANSITION DISABLED)
Figure 9. REFIN Transition (Skip Mode, Downward Transition Disabled)
Table 3. DTRANS Operating Modes Truth Table
DTRANS X SKIP_ H OPERATION DURING TRANSITION SKIP_ sets the respective phase in forced-PWM mode. All positive and negative REFIN transitions are forced. PGOOD_ is blanked during the SLEW_ capacitor transition + 20s. SKIP_ sets the respective phase in pulse-skipping mode. Negative REFIN transitions are not forced, and the output voltage is discharged by the load. SKIP_ sets the respective phase in pulse-skipping mode. All positive and negative REFIN transitions are forced. PGOOD_ is blanked during the SLEW_ capacitor transition + 20s.
H
L
L
L
20
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Dual and Combinable Graphics Core Controller for Notebook Computers
While ON2 is low, PGOOD2 is blanked high impedance. When ON2 goes high again, the PGOOD2 current-balance comparator is reenabled. Adaptive dead-time circuits monitor the DL_ and DH_ drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX8775 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.6 (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges, do not pull up the low-side MOSFETs' gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFETs' gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Adding a resistor less than 10 in series with BST_ might remedy the problem by increasing the turn-on time of the high-side MOSFET without degrading the turn-off time.
MAX8775
Current Balance (CCI2) CCI2 is the output of the current-balance transconductance amplifier. The voltage level on CCI2 allows fine adjustment to the duty cycle of phase 2, keeping phase 2's current in balance with phase 1. When VCCI2 is 20% above or below VREF, PGOOD2 goes low, indicating the currents in the two phases are not balanced.
Place a 47pF capacitor from CCI2 to AGND to integrate the current balance error. CCI2 is clamped to REF when ON2 is low. CCI2 is unused in separate mode, and can be left unconnected.
Current-Limit Protection
The current-limit circuit uses differential current-sense inputs (CSH_ and CSL_) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold, the PWM controller turns off the high-side MOSFET (Figure 3). At the next rising edge of the internal oscillator, the PWM controller does not initiate a new cycle unless the current-sense signal drops below the current-limit threshold. The actual maximum load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (VOUT/VIN). In forced-PWM mode, the MAX8775 also implements a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately -120% of the positive current limit and tracks the positive current limit. The current limit is fixed at 30mV (typ).
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output of a comparator that continuously monitors each SMPS output voltage for overvoltage and undervoltage conditions. PGOOD_ is actively held low in shutdown (ON_ = GND), soft-start, and soft-shutdown. Once the soft-start terminates, PGOOD_ becomes high impedance as long as the output does not drop below 150mV from the nominal regulation voltage set by REFIN_. PGOOD_ goes low once the output drops 150mV below its nominal regulation point, an output overvoltage fault occurs, or ON_ is pulled low. For a logic-level PGOOD_ output voltage, connect an external pullup resistor between PGOOD_ and +5V or +3.3V. A 100k pullup resistor works well in most applications. PGOOD_ is blanked high impedance during all transitions detected at REFIN_ until 20s after the output reaches the regulation voltage.
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MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN V OUT differential exists. The high-side gate drivers (DH_) source and sink 2A, and the low-side gate drivers (DL_) source 1.7A and sink 3.3A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by charge pumps at BST_ while the DL_ synchronous-rectifier drivers are powered directly by the external 5V supply (VDD).
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Dual and Combinable Graphics Core Controller for Notebook Computers
In combined mode (REFIN2 = V CC), PGOOD1 indicates the output voltage is in regulation, while PGOOD2 indicates the currents between the two phases are in balance. PGOOD2 is the output of a comparator that monitors the voltage difference between CCI2 and REF. Since CCI2 is the output of a transconductance amplifier, even small current imbalance over a long time causes CCI2 to go high or low, depending on the current imbalance. Whenever CCI2 is 20% above or below REF (CCI2 3V or CCI2 2V), PGOOD2 goes low, indicating the currents in the two phases are not balanced. PGOOD2 is blanked high impedance during all transitions detected at REFIN_ until 20s after the output reaches the regulation voltage.
MAX8775
In combined mode (REFIN2 = VCC), OVP1 sets the overvoltage fault threshold for the combined output, while OVP2 is connected to REF when OVP is enabled, and to VCC when OVP is disabled.
Fault Protection
Output Overvoltage Protection The MAX8775 includes an OVP_ pin that allows flexible setting of the overvoltage fault threshold. The overvoltage threshold is 200mV (typ) above the voltage at the OVP_ pin. This simplifies the configuration, allowing the OVP_ pin to be directly connected to REFIN_, eliminating the need for extra resistors to set the overvoltage level. If the output voltage of either SMPS rises 200mV above its nominal regulation voltage, the corresponding controller sets its overvoltage fault latch, pulls PGOOD_ low, and forces DL_ high for the faulted side. The other controller is not affected. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the battery fuse blows. Cycle VCC below 1V or toggle both ON_ pins to clear the overvoltage fault latch and restart the SMPS controller.
Output Undervoltage Protection If the output voltage of either SMPS falls 300mV below its regulation voltage, the corresponding controller sets its undervoltage fault latch, pulls PGOOD_ low, and begins soft-shutdown for the faulted side by pulsing DL_. DH_ remains off during the soft-shutdown sequence initiated by an undervoltage fault. The other controller is not affected. After soft-shutdown has completed, the MAX8775 forces DL_ high and DH_ low. Cycle VCC below 1V or toggle ON_ to clear the undervoltage fault latch and restart the SMPS controller. VCC POR and UVLO Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the PWM for operation. VCC undervoltage-lockout (UVLO) circuitry inhibits switching, forces PGOOD_ low, and forces the DL_ gate drivers low. If VCC drops low enough to trip the UVLO comparator while ON_ is high, the MAX8775 immediately forces DH_ and DL_ low on both controllers. The output discharges to 0V at a rate dependent on the load and the total output capacitance. This prevents negative output voltages, eliminating the need for a Schottky diode to GND at the output.
Table 4. Operating Modes Truth Table
MODE Power-Up Run Output Overvoltage Protection (OVP) CONDITION VCC UVLO ON1 or ON2 enabled Either output > 200mV above nominal level Either output < 300mV below nominal level, UVP is enabled 6144 clock cycles (1/fOSC) after the output is enabled (ON_ going high) ON1 and ON2 are driven low TJ > +160C DESCRIPTION When ON_ is high, DL_ is forced low as VCC falls below the 3.95V (typ) falling UVLO threshold. DL_ is forced high when VCC falls below 1V (typ). Normal operation. When the overvoltage comparator trips, the faulted side sets the OV latch, forcing PGOOD_ low and DL_ high. An OV fault on one SMPS does not affect the operation of the other SMPS. The OV latch is cleared by cycling VCC below 1V or cycling both ON_ pins. When the undervoltage comparator trips, the faulted side sets the UV latch, forcing PGOOD_ low and initiating the soft-shutdown sequence by pulsing only DL_. DL_ goes low after soft-shutdown. A UV fault on one SMPS does not affect the operation of the other SMPS. The UV latch is cleared by cycling VCC below 1V or cycling the respective ON_ pin. DL_ stays low after soft-shutdown is completed. All circuitry is shut down. Exited by POR or cycling ON1 and ON2. DL1 and DL2 remain low.
Output Undervoltage Protection (UVP)
Shutdown Thermal Shutdown
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Dual and Combinable Graphics Core Controller for Notebook Computers
Thermal-Fault Protection The MAX8775 features a thermal-fault protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latches, pulls PGOOD_ low, and shuts down both SMPS controllers using the soft-shutdown sequence (see the Soft-Start and SoftShutdown section). Cycle VCC below 1V or toggle ON1 and ON2 to clear the fault latches and restart the controllers after the junction temperature cools by 15C.
Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 30% ripple current. When pulse skipping (SKIP_ low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs.
MAX8775
Inductor Selection
The per-phase switching frequency and inductor operating point determine the inductor value as follows: VOUT (VIN - VOUT ) L= VINfOSCILOAD(MAX)LIR For example: ILOAD(MAX) = 15A, VIN = 12V, VOUT = 1.5V, fOSC = 300kHz, 30% ripple current or LIR = 0.3: L= 12V x 300kHz x 15A x 0.3 1.8V x (12V - 1.8V ) = 0.97H
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum Load Current. There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor Operating Point. This choice provides trade-offs between size and efficiency and between transient response and output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load).
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: IINDUCTOR = VOUT (VIN - VOUT ) VINfOSCL
Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + IINDUCTOR 2
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur: VSAG = 2COUT (VIN x DMAX - VOUT ) ILOAD(MAX) (T - T) COUT where D MAX is the maximum duty factor (see the Electrical Characteristics), T is the switching period (1 / f OSC), and T equals V OUT / V IN x T when in PWM mode, or L x 0.2 x IMAX / (VIN - VOUT) when in skip
23
*
*
L( ILOAD(MAX) )
2
+
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
mode. The amount of overshoot during a full-load to noload transient due to stored inductor energy can be calculated as: VSOAR The current-sense method (Figure 10) and magnitude determine the achievable current-limit accuracy and power loss. The sense resistor can be determined by: RSENSE_ = VLIM_ / ILIMIT_ For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 10a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. However, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. This parasitic inductance (LESL) can be cancelled by adding an RC circuit across the sense resistor with an equivalent time constant: L CEQREQ = ESL RSENSE Alternatively, low-cost applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 10b) with an equivalent time constant:
(ILOAD(MAX) )2L
2NPHCOUT VOUT
where NPH is 2 in combined mode when both phases are active.
Setting the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The perphase peak inductor current occurs at ILOAD(MAX) plus half the ripple current; therefore: ILIMIT > ILOAD(MAX) IINDUCTOR + NPH 2
where NPH is 2 in combined mode, and ILIMIT equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE_). For the 30mV default setting, the minimum current-limit threshold is 26mV.
INPUT (VIN) DH_ LX_ NH CIN L SENSE RESISTOR LESL RSENSE CEQREQ = NL DL REQ CEQ COUT LESL RSENSE
MAX8775 DL_
PGND CSH_ CSL_
a) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH_ LX_ NH CIN L INDUCTOR RDCR RCS = NL DL R1 R2 CEQ COUT L RDCR = C EQ 11 [ R1 + R2 ] R2 = R DCR R1 + R2
MAX8775 DL_
PGND CSH_ CSL_
b) LOSSLESS INDUCTOR SENSING
Figure 10. Current-Sense Configurations
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Dual and Combinable Graphics Core Controller for Notebook Computers
R2 RCS = RDCR R1+ R2 and: RDCR = L 1 1 x + CEQ R1 R2
Output Capacitor Stability Considerations Stability is determined by the value of the output zero relative to the switching frequency. The boundary of instability is given by the following equation: f RESR < 2RSENSE and fESR SW
where: fESR = 1 (2RESR + 4RSENSE )COUT
MAX8775
where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see stability requirements), the filter capacitor's ESR dominates the output voltage ripple. Therefore, the output capacitor's size depends on the maximum ESR required to meet the output voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P-P) = RESRILOAD(MAX)LIR In Idle Mode, the inductor current becomes discontinuous, with peak currents set by the Idle Mode current-sense threshold (VIDLE = 0.2VLIMIT). In Idle Mode, the no-load output ripple can be determined as follows: V R VRIPPLE(P-P) = IDLE ESR RSENSE The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high ESR zeros that may affect the overall stability (see the Output Capacitor Stability Considerations section).
For a typical 300kHz application, the output zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mV P-P ripple is 25mV/1.5A = 16.7m. One 330F/2.5V Sanyo polymer (TPE) capacitor provides 7m (max) ESR. Together with the 1.5m currentsense resistors, the output zero is 25kHz, zero is 25kHz, well within the bounds of stability. The MAX8775 is optimized for low-duty-cycle operations. Steady-state operation at 45% duty cycle or higher is not recommended. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the RMS ripple current requirement (IRMS) imposed by the switching currents. For a single step-down converter, the RMS input ripple current is defined by the output load current (IOUT), input voltage, and output voltage, with the worst-case condition occurring at VIN = 2VOUT: IRMS = IOUT VOUT (VIN - VOUT ) VIN
For a dual +180 interleaved controller, the out-ofphase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements. When both outputs operate with a duty cycle less than 50% (VIN > 2VOUT), the RMS input ripple current is defined by the following equation:
V V IRMS = OUT1 IOUT1(IOUT1 - IIN ) + OUT2 IOUT2 (IOUT2 - IIN ) VIN VIN
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
where IIN is the average input current: V V IIN = OUT1 IOUT1 + OUT2 IOUT2 VIN VIN In combined mode (REFIN2 = VCC) with both phases active, the input RMS current simplifies to: V 1 V IRMS = IOUT OUT - OUT VIN 2 VIN For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. Choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime. V PD (NH Resistive) = OUT (ILOAD )2RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: VIN(MAX)ILOADfSW QG(SW) PD (NH Switching) = IGATE IGATE + COSSVIN(MAX)2fSW 2
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, optimum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderatesized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX8775 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drainto-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.
where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: V 2 PD (NL Resistive) = 1- OUT (ILOAD ) RDS(ON) VIN(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX), but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate:
Power-MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage:
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Dual and Combinable Graphics Core Controller for Notebook Computers
I ILOAD = ILIMIT - INDUCTOR 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time.
Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (IDOWN) as much as it ramps up during the on-time (IUP). This results in a minimum operating voltage defined by the following equation:
1 VIN(MIN) = VOUT + VCHG + h - 1 (VOUT + VDIS ) DMAX where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1.
MAX8775
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = QGATE 200mV
where QGATE is the total gate charge specified in the high-side MOSFETs' data sheet. For example, assume the SI7634DP n-channel MOSFET is used on the high side. According to the manufacturer's data sheet, a single SI7634DP has a gate charge of 21nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 13nC = 0.105F 200mV
Maximum Input Voltage The MAX8775 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP_. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an ontime pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)):
1 VIN(SKIP) = VOUT fOSCt ON(MIN) where fOSC is the switching frequency selected by OSC.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCB (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters,
27
Selecting the closest standard value, this example requires a 0.1F ceramic capacitor.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
where a single m of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_). When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST_ capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1, 2, and 11. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
*
* Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, REFIN_, CSH_, CSL_).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, COUT_, and DL_ anode). If possible, make all these connections on the top layer with wide, copper-filled areas.
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (SEE EVALUATION KIT) KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (SEE EVALUATION KIT)
RSENSE INDUCTOR
OUTPUT 2
OUTPUT 1
RSENSE INDUCTOR
COUT
POWER GROUND
COUT CIN
PHASE 2
COUT
PHASE 1 VIA TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND REF BYPASS CAPACITOR
COUT
CIN
INPUT VCC BYPASS CAPACITOR VIA TO ANALOG GROUND
CONNECT GND AND PGND THE CONTROLLER AT ONE POINT ONLY AS SHOWN
Figure 11. PCB Layout
Chip Information
TRANSISTOR COUNT: 6372 PROCESS: BiCMOS
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Dual and Combinable Graphics Core Controller for Notebook Computers MAX8775
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.

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